!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!! FINAL SPEC 7xmem 32bit !!! XSPI OCTO "SSD" will be SEPARATE as FAST "7xdsk" (DDR2-20+GND = short part of DDR2 socket)
!!! 7xmem can hold SRAM+SDRAM combo, externally 2banks of SRAM and 2banks of SDRAM
!!! 7xmem can hold also SRAM only memory, with internal banking/decoder for SRAM MORE chips
!!! 7xmem can hold also SDRAM only memory, but here without CPLD CKE multiplexing, no way to have more than 2 banks (?)

FAST              SLOWER
DDR2-80+GND       2x40_50mil (GND only inline + mosfets)
===========       ==========

00 D31               D31 D30         - DATA32 (damp 33 all) (DIP32+16 "RAISER": pullups + 2x GND = 16bit SRAM ONLY)
01 D30               D29 D28
02 D29               D27 D26
03 D28               D25 D24
04 D27               /B3 GND
05 D26               D23 D22
06 D25               D21 D20
07 D24               D19 D18
08 /B3 DQM3          D17 D16
09 GND               /B2 GND
-

10 D23
11 D22
12 D21
13 D20
14 D19
15 D18
16 D17
17 D16
18 /B2 DQM2
19 GND
-     --- (DIP32+16 "RAISER": pullups + 2x GND = 16bit SRAM ONLY)

20 D15               D15 D14         - DATA16 (damp 33 all) (+ 2x GND)
21 D14               D13 D12
22 D13               D11 D10
23 D12               D09 D08
24 D11               /B1 GND
25 D10               D07 D06
26 D09               D05 D04
27 D08               D03 D02
28 /B1 DQM1          D01 D00
29 GND               /B0 GND
-

30 D07
31 D06
32 D05
33 D04
34 D03
35 D02
36 D01
37 D00
38 /B0 DQM0
39 GND
-

40 /SDCLK            /SDCLK   /OE    - CTRL ( damp 33 all + VCC + GND + "sdram quiet addr gnd" )
41 /OE               /SDCKE0  /SDCKE1
42 /SDCKE0           /SDE0    /SDE1         ( 7xsys: /SDE0 NOR /SDE1 => /E0 /E1 mosfet to GND => 7xmem: /E0 NAND /E1 => XOR / NO SRAM chip-selected )
43 /SDCKE1           /SDCAS   /SDRAS
44 /SDE0             /SDWE    /WE
45 /SDE1             SCL+VCC  SDA+GND       ( 7xsys after POST: mosfet to VCC/GND 47k pullup, 4k7 damp )
46 /SDCAS            A23      A22           ( sdram quiet gnd ?? sram banking ?? )
47 /SDRAS            A21      A20           ( sdram quiet gnd ?? sram banking ?? )
48 /SDWE             A19      A18           ( sdram quiet gnd ?? )
49 /WE               A17      A16           ( sdram quiet gnd ?? )
- ---

50 SCL (mosfet VCC)
51 SDA (mosfet GND)
52 A23
53 A22
54 A21
55 A20
56 A19
57 A18
58 A17
59 A16
-
60 VCC               VCC /E0+GND     - ADDR ( VCC + /E0 /E1 mosfet to GND during SDRAM access - damp 33 all )
61 /E0 (mosfet GND)  A15 A14                ( sdram BA1 BA0 )
62 A15 /BA1          A13 A12
63 A14 /BA0          A11 A10
64 A13               A09 A08
65 A12               VCC /E1+GND            ( VCC + /E0 /E1 mosfet to GND during SDRAM access - damp 33 all )
66 A11               A07 A06
67 A10               A05 A04
68 A09               A03 A02
69 A08               A01 A00
-
70 VCC
71 /E1 (mosfet GND)
72 A07
73 A06
74 A05
75 A04
76 A03
77 A02
78 A01
79 A00

( DDR2 bottom "GND-wall" MAY include also FEW (6) additional VCC pins - under each top true GND or VCC )
( it is expected there will be ONE 7xmem SHARED VCC, tweakable by EEPROM ID, so 3V3 default, but also ANY from 7xsys, so 2V5. 1V8 ... )
( SLOWER 2x40pin 50mil connector MAY (??) use special mode of /E0 /E1 (SRAM CS) when BOTH are GND (by mosfets) then SRAMs forced unselected... for SAFER SDRAM CTRL signaling (?) )
( SRAM or SDRAM "only" modules can have "forced quiet gnd or 7xsys mosfets" on unused CTRL pins too )
( in SLOWER connector mode (33/22 MHz), additional GND may be also unnecessary (?) )