KiCad V5 !!! - learning - based on BEST Johns Basement tutorial =================================================================== IF YOU REALLY WANT TO GO TO V6, READ AT LEAST THIS FIRST INTRO: https://www.circuitstate.com/tutorials/how-to-install-kicad-version-6-and-organize-part-libraries/ https://www.circuitstate.com/tutorials/getting-started-with-kicad-version-6-beginners-tutorial-to-schematic-and-pcb-design/ V6 VIDEO SIMPLE/SCRATCHING TUTORIAL (good to skip quickly) https://www.youtube.com/playlist?list=PLmzKTn3f9uzGb6O5gMRJf5Sur7RGk0jTR - as checked recently KiCad V6/V7 HAS NOT even installed GREAT multilanguage HELP locally !!! - V6+ has somewhat simplified schema-to-pcb (and backwards) process, but it seems LESS INTUITIVE (???) - FACT IS, THAT V6+ "DRAG FOOTPRINT" feature (D) is very usefull !!! - V5 has BETTER LOOKING color tools icons !!! (any yes, matches to this tutorial) - John is not using autorouter, as KiCad V5 (dont know how V6/V7) doesnot support "pin swaping", making autorouter less smart ... - yes, for V6+ exists that JLCPCB integration plugin, okay BASIC PCB LAYOUT - based on VIDEO #4 (65 minutes) https://www.youtube.com/watch?v=xmoT7CherYU&list=PL3by7evD3F51fKkyrUbH-PCdwPCWc9F8a&index=4 ----------------------------- keyboard Ctrl+S - save ALT-3 - 3D preview R - rotate M - move E - edit lock pads vs lock footprint F - flip Q - traces/vias width G - drag parts/traces (V6 footprints !!!) B - refill copper zones V - place VIA D - drag VIA (??????????? isnt this in fact "G" ??? lisen again !!!!!!!, TRY IT YOURSELF !!!!) U - select trivial connection (more press select more) ??? I - select ENTIRE copper connection grid edge dimensions in mm or by requirements to fit footprints placing at lower 0.25mm ? layers FCu - draw - copper traces/vias + filled zones (E =properties (GND), draw rect outside edge, do for both layers) Bcu FSilks - draw - text (thickness down to 0.1mm ONLY for OSHPark), also "footprint as OSHW logo" (but add also OWN copyright) (not over vias) BSilks Dwg User - draw - dimensions here Edge Cuts - draw - graphic lines - yellow line (board edge here) - ESC to end last segment, !! place GND vias (0.4mm) around the "fill zoned" board edge for HF design !! menu - design rules defaults !! do DRC (BUG ICON) - unconnected lines / refilling fones ??? mess ... PRECISE MFG DEFAULTS AND BOARD OUTLINE - based on VIDEO #5 (35 minutes) https://www.youtube.com/watch?v=X86HUpOr_g8&list=PL3by7evD3F51fKkyrUbH-PCdwPCWc9F8a&index=5 ---------------------------------------------------------------------------------- - OSHPark web design rules -- !!! not applicable for china JLCPCB, PCBWAY !!! layers FMask - precise clearance menu - pads to mask clearance menu - design rules editor (global, net classes) - track width, clearance, via dia, via drill copper zones, select and "E" edit - clearances, parameters !!! - clearance, width, antipad clearance, spoke width - SOLDERING BY HAND ==>> default pad connection = THERMAL RELIEFS (spaces in connections to filled zones) !!! - separate "E" edit for front and bottom copper zoones !!! (0.2 0.2 0.2 0.75 OSHPark) board edges from copper zones - from center of yellow lines !!! "E" edit line segment properties to 0.4 (=> 0.2 width 0.2 clearance - OSHPark 0.4 edge !!!) - "B" to refill zones polygons board dimension - left side "inch mode" - layer DwgsUser, draw dimensions - JOHN mentions cheaper SHIPPING for US from OSHPark for smaller boards, for EU its better from china still !!!! - OSHPark GOLD plating, PCBWAY faster, only HASL finish, but for super tiny hotair soldering, GOLD is better !!! board outline change - layer EdgeCuts - draw lines - "B" to refill GND polygons - select and move all GND vias on edited edge - layer silkscreen - unlock and edit OSHPark - direct KiCad pcb files upload and CHECK !!! VIA CLEANUP - based on VIDEO #6 (8 minutes) https://www.youtube.com/watch?v=RDo-9NjxDDs&list=PL3by7evD3F51fKkyrUbH-PCdwPCWc9F8a&index=6 ------------------------------------------------------------------------------------------ - filling zones by copper for THERMAL reasons !!! => no (or even) thermal stress for FR4 PCB =>more efficient for MFG by etching less copper - left panel SHOW/HIDE filled zones - PLACING GND VIAS AROUND BLOCKING CAPACITORS for better electrons current flow over them !!! - beware of VIAS accidentally shortening to bottom GND (no sense to placing them on NON GND !!!) - hit "B" to refill zones FANCY BOARD OUTLINE - based on VIDEO #7 (6 minutes) https://www.youtube.com/watch?v=prI58doQT40&list=PL3by7evD3F51fKkyrUbH-PCdwPCWc9F8a&index=7 -------------------------------------------------------------------------------------------- - rounded edges of board outline - layed EdgeCuts - draw ARCS, hit "B" to refill GND zones polygons SILKSCREEN TEXT AND PNG GRAPHIC - based on VIDEO #8 (12 minutes) https://www.youtube.com/watch?v=Ebc4jl4K4HY&list=PL3by7evD3F51fKkyrUbH-PCdwPCWc9F8a&index=8 --------------------------------------------------------------------------------------------- - graphic may not be free, on OSHPark is free OSHW logo drawing - layer BSilks - placing hyperling and another OSHW logo - looks MIRRORED by view on the layers from top, hit ALT-3 to show 3D preview !!! - placing OSHW logo by "F" flipping it to BSilk layer !!! - searching right OSHW logo footprint size - adding VERSION id to the FSilks layer DIGIKEY SYMBOL & FOOTPRINT LIBS - based on VIDEO #9 (9 minutes) https://www.youtube.com/watch?v=yuRGPwp3mSQ&list=PL3by7evD3F51fKkyrUbH-PCdwPCWc9F8a&index=9 --------------------------------------------------------------------------------------------- - github "digikey kicad" ONLY FOR V5 ??? (https://github.com/Digi-Key/digikey-kicad-library) (also https://github.com/Digi-Key/digikey-partner-kicad-library) - KICAD SCHEMA - menu Preferences - Manage Symbol libraries - Browse libs "DIGIKEY downloaded" - symbols, select all, OPEN (dk_) - menu FOOTPRINT EDITOR - menu Preferences . Mange Footprint libraries - Browse libs "DIGIKEY downloaded", OK - place PARTS from right panel - example "dsub" - offers 2 "dk_*" parts SCHEMA + PCB DESIGN REVISIONS - based on VIDEO #10 (35 minutes) https://www.youtube.com/watch?v=EHaO1nhgoJA&list=PL3by7evD3F51fKkyrUbH-PCdwPCWc9F8a&index=10 --------------------------------------------------------------------------------------------- - changing PWR plug to USB by maintaining PART REFERENCE, but changing SYMBOL ID - "E" for Symbol properites - new one - menu "Netlist" - generate netlist - footprint selection - reference the "SymbolID" on schema to stay the same - TIMESTAMP !!! for better changes, to Keep/Keep/Keep ... - when SYMBOL ID changes, then Netlist footprint REFERENCE, echange footprint CHANGE !!!!!!!!!!! - read current netlist - REMOVING 5V regulator here, not anymore needed - USB pins are all "passive" so we need to at +5V NET - power lines must be connecte to PWR FLAG !!! - adding 2 more header connectors - placing Xes (from right panel) to unconnected pins - menu "Assign PCB footprints" - new connector had NO footprints so "E" Symbol Properties - Footprint - Browse (Library) - menu "NEW Netlist" - Generate Netlist - KICAD PCB - menu Netlist - "Read Current Netlist" - menu Netlist - "Extra Footprints" DELETE - !!! things which ARE NOT IN SCHEMATIC WILL DISAPPEAR, AS "OSHW" graphics logo !!!!!!!!!! !!! to save them in netlist, they must be placed ALSO into schematic !!!!!!!! - IN THIS CASE, ENTIRE BOARD WILL BE REROUTED MANUALLY !!!!!!!! too much changes !!!!!!!!!!! - note CAPS put also into 2x2 headers pins footprint !!! ))) - board outline is SMALLER also - bord bottom uses some traces also, but its still filled then by "B" by copper zones !!! REVISING REVISIONS - based on VIDEO #10a (7 minutes) https://www.youtube.com/watch?v=dEA3SUgA_84&list=PL3by7evD3F51fKkyrUbH-PCdwPCWc9F8a&index=11 ---------------------------------------------------------------------------------------------- - missing GND links at output schoma (Vout nets marked by correcponding connectors, they are swichable by JUMPERS !!!) - added some BLOCKING CAPS VIAs around them - CALIPER TOOL (right panel) - precise measure distances for placing USB connecto to the edge !!! (or press SPACE to place zero mouse reference show dx/dy on status bar to see mouse difference) - starting over the new PCB layout - possible Global Delete ALL TRACKS too !!! (menu Edit - Global Deletions ...) - mentioning HOTKEY editor to see another keys: - "U" to select trivial connection - "I" to select ENTIRE copper connection (??? s NOT mapped in V6/V7 ??? - multiple "U" works ???) BUILD AND TEST BOARD - based on VIDEO #10b (4 minutes) https://www.youtube.com/watch?v=zaHardupIT0&list=PL3by7evD3F51fKkyrUbH-PCdwPCWc9F8a&index=12 ------------------------------------------------------------------------------------------------ - showing how to solder tiny microUSB and how was 2x5 headers modified to place board flat on breadboard !!! CREATING NEW SYMBOLS - based on video #11 (23 minutes) https://www.youtube.com/watch?v=wKK0anE3pKo&list=PL3by7evD3F51fKkyrUbH-PCdwPCWc9F8a&index=13 ---------------------------------------------------------------------------------------------- - creating breakout board for 48pin NXP LPC51U68 - create any new empt kicad project (required still in V6 ??) - KICAD "Symbol Library Editor" - modify existing digikey library, base on template - menu - create new library (global) - here named "jb-symbol" (pair of LIB+DCM files) - right click new emty librby - "New symbol..." - Symbol name - use FULL part name, including number of pins, to later IDENTIFY it !!! - right click - select GRID (Johns preference 100mils, most symbols done in 50mils) - place datasheet symbol image aside to mimic the pins order - right panel - place "Add pins to symbol" - select PIN NAME, NUMBER, ORIENTATION, ELECTRICAL TYPE, GRAPHIC STYLE - PIN NUMBER is CRUCIAL for DRC and NETLIST !!! other NAME is only HUMAN ID - check all the pins carefully - rigth panel "Add graphic rectangle" to mace actual rect symbol with pins - click on rectangle to select and hit "E" to edit, select FILL BACKGROUND (will be yellow) - menu "Symbol Properties" - Description from datasheet !!! - edit ALIAS LIST for alternative human names to be selected for by searching libraray - alterantivelly edit also "footprint filter" . menu "Symbol Fields" - Footprint !!! - browse for datasheet based one (here QFP 7x7 48pin 0.5mm pitch) - Datasheet !!! - DIGIKEY and MOSUER part id here too - to order it !!! - TEST new part in schematic - connect some list, no DRC, menu Netlist "Generate Netlist" - open PCB editor, Netlist "Read Current netlist" - check ALT+3 3D view ... CREATING NEW FOOTPRINTS - based on VIDEO #12 (20 minutes) https://www.youtube.com/watch?v=Rdm5lS_sYsc&list=PL3by7evD3F51fKkyrUbH-PCdwPCWc9F8a&index=14 ---------------------------------------------------------------------------------------------- - select and place some similar symbol in existing library, to have at least similar function in schematic - "E" symbol properties and delete/update all digikey fields (Symbol libraray uses pair of LIB+DCM to be defined - Footprint libraray uses different approach, in fact subfolder with all the footprints) - PCB editor: - menu "New Footprint" - name it as the SYMBOL PART NAME - menu "Create new library" - select placement folder in your user libraries - and append to path NAME OF LIBRARY (in the target folder is created NAME.pretty subfolder for all the footprints in it - here "jb-footprint.pretty") (in this new library folder is new footprint file as "NAME.kicad_mod") - check that new footprint library is in menu - Preferences - "Manage footprint libraries" !!! (footprint libs are NOT auto added) - in dialog select "Browse libraries..." and find that *.pretty folder and select it there - show datasheet footprint picture/dimensions aside and start placing: - set GRID to proper pads placing by dimensions - from right panel "Add pads" and consider CENTER of entire footprint as X=0 Y=0 coordinates - place FIRST pad around that virtual CENTER of entire footprint - EDIT placed pad to properly set his properties according to picture/dimensions - Hole size = 1mm + Size = 1.7 for circular one as here - this is hoe KiCad usualy sizes such solder hole - select SHAPE for pin 1 as RECTANGULAR - now, placing any additional pins will use such edited pin defaults for more of them - EDIT pad again to select CIRCULAR for next pads - SAVE new edited fottprint back into jb-footprint library (must be selected ???) - now start drawing the outer edges (courtyard) of footprint (here it is rectangle around pins, but it is off-centered so it needs to be properly placed) - hit "SPACE" key with mouse at PIN 1 center to RESET coordinates to exactly measure displacemnt (use even slightly off GRID to make footprint slightly LARGER than actual drawing) - check layer FSilks and select "Add graphic line" and draw first one based on dimensions - hit "SPACE" at corners to roperly measure dimensions of rectangle lines - redraw the edges rectangle also exactly in layer FCrtYd (courtyard) - SAVE COPYING/ALTERING SYMBOLS - based on VIDEO #13 (7 minutes) https://www.youtube.com/watch?v=rE4tIZbz9C4&list=PL3by7evD3F51fKkyrUbH-PCdwPCWc9F8a&index=15 ---------------------------------------------------------------------------------------------- - using example datasheet of specific "1P 2S" transformer to customize generic one and renumber and rename pins - select existing symbol in "symbol library editor" - right click and select "Copy Symbol" - search for your user libary and select it - select your librbrary - right click and select "Paste Symbol" there - RENAME your custom symbol in your library to something more specific (actual PART NAME) - menu Symbol - Properties - edit show/hide symbol pin numbers and names !! - RENUMBER pins to match those in datasheet - ADD MISSING PINS changing their electrical type to "NC" as "not visible" - EDIT generic description of symbol to the datasheet specific one (you may also edit "keywords" and "aliases" to find symbol easily later) CREATING FOOTPRINT WITH SLOTTED HOLES (non circular) - based on VIDEO #14 (20 minutes) https://www.youtube.com/watch?v=vHPh-SJe9XA&list=PL3by7evD3F51fKkyrUbH-PCdwPCWc9F8a&index=16 --------------------------------------------------------------------------------------------- - using example THT 3.5mm jack connector - select audio jack from symbols libraray and place it into empty schematic - CTRL+"E" at symbol to EDIT his definition to add PIN NUMBERS - modify symbol pin numbers according to the actual datasheet ?? they can stay as letters, "TRS" here - open FOOTPRINT EDITOR - select "jb-footprint" library - menu "New footprint" and put NAME according to datasheet part name - place first pad and EDIT pad proeprties: - Hole shape: OVAL (slotted) - hole size X=2 size Y=1 - shape OVAL size X=3.5 size Y=2.5 - palce and rotate all (3) other slotted holes, marked by pin number as "TRS" - in layer FSilks draw all the exact edges + other - in layer FCrtYd draw rectangular edges of "courtyard" (always rectangle, may be even over ENTIRE edges) NET NAMES, BUSES, NETLIST FILE - based on VIDEO #15 (24 minutes) https://www.youtube.com/watch?v=B59n6eJzxMU&list=PL3by7evD3F51fKkyrUbH-PCdwPCWc9F8a&index=17 ----------------------------------------------------------------------------------------------- - NETLIST (.NET) IS THE ONLY THING THAT FLOWS FROM SCHEMA EDITOR (.SCH) TO PCB EDITOR (.KICAD_PCB) !!! - right panel "Highlight net" to "pink" net lines - right panel "Net name" to name net (virtually connecting the wires in fact) - in case you MUST name net, dont use special chars as ()[]/ etc, use alpha-num-underscore, as "identifiers" - use tilda ~ to prefix NEGATIVE nets/pins - in .NET file, anything named with "/" prefix is LOCAL net (useful in multiple sheets schematic) - right panel "WIRE" or "WIRE TO BUS ENTRY" are GREEN - right panel "BUS" or "BUS TO BUS ENTRY" are BLUE (!!! beware weird behavior f bus-to-bus, see below) - right panel "X" is "not connected" - right panel "DOT" is explicit junction between wires or buses - HOW BUSes work: - name nets for buses as for example A[1..4] (for wires - A1 A2 A3 A4) - "INSERT" key places another wires/names under the first horizontal one - as example 4pin connector with A1,A2,A3,A4 - place "WIRE TO BUS ENTRY" from connector pins to bus - possible to assign more net names to BUS, as A[1..4] and B[1..4] - DO NOT place "BUS TO BUS ENTRY" instead of BUS junction point (possible to "rotate" is with context menu as "Bus to bus SHAPE /") (!!! if you want to have busses CONNECTED !!!) - !!! USE JUNCTION TO CONNECT TWO/MORE BUSES !!! MULTISHEET SCHEMATICS - based on VIDEO #16 (20 minutes) https://www.youtube.com/watch?v=B59n6eJzxMU&list=PL3by7evD3F51fKkyrUbH-PCdwPCWc9F8a&index=17 ---------------------------------------------------------------------------------------------- - sheet title shows Sheet: x / y - menu "Sheet navigator" shows "root" - right panel "Create Hierarchical sheet" to place one on root sheet (has SHEET name and FILE name) - KICAD base dialog shows original "multisheet.sch" and also new "power.sch" as part of "multisheet.pro" (project) - menu "Sheet Navigator" show hierarchy of Root-Power - sheets title shows appropriate sheet name and numbering - menu - "Append Schematic Sheet..." - (Power supply) - menu "Edit Page Settings" to US Letter to properly align copied sheet to the frame with title etc... - right panel "Create Hierarchical sheet" to place one on root sheet (has SHEET name and FILE name) - menu - "Append Schematic Sheet..." - (MIC Preamp) - "E" to edit name as MIC1 - right panel "Create Hierarchical sheet" to place one on root sheet (has SHEET name and FILE name) - menu - "Append Schematic Sheet..." - (MIC Preamp) - "E" to edit name as MIC2 - now solve GLOBAL vs LOCAL net names to CONNECT hierarchical subsheets together - first - menu "Anontate schematic" ... "sheet number x 100" to separatelly number parts on identical sheets imported twice or more !!! - "modular" imported schematics have NO NET NAMES at the input/output terminals, there is JUST PLAIN TEXT ONLY - instead on "Name net" tool, use "Place global label" to name net globally !!! - place on ROOT sheet global labels as INPUTs - MIC_OUT1 and MIC_OUT2 (linked from hierarchical subsheets MIC1 and MIC2 outputs) - connect such inputs to the board connector - EDIT title block / page properties of ROOT SHEET by checking "export to other sheets" in dialog (Issue date, Revision, Title, Company ...) - now in KICAD PCB EDITOR: - check ALT+3 to see all footprints placed in 3D view (its all aligned by separate sheets, but of course NOT properly layed out) FLAT MULTISHEET DESIGN - based on VIDEO #16a (3 minutes) https://www.youtube.com/watch?v=B5OG4EuQnI8&list=PL3by7evD3F51fKkyrUbH-PCdwPCWc9F8a&index=19 ---------------------------------------------------------------------------------------------- - hierarchical sheets placed OUSIDE of main sheet (they will not be printed into PDF of root) HIERARCHICAL LABELS & PINS - based on VIDEO #17 (18 minutes) https://www.youtube.com/watch?v=m_HTBurAJn4&list=PL3by7evD3F51fKkyrUbH-PCdwPCWc9F8a&index=20 ----------------------------------------------------------------------------------------------- - (refereing to #16 MULTISHEET SCHEMATICS) - similar to global vs local identifiers in programming languages - right panel "Place hierarchical label" (in total 4 icons there) - power +5V / VCC / GND are by default global names too (may be not always wanted also) - so REMOVE all connecting "global labels" placed into original multisheet schematic now - place "hierarchical labels" equally named as "out" to BOTH MIC1 and MIC2 subsheets, they are LOCAL there - ... "pins" go to the symbols, "labels" go to the sheets - right panel "Place hierarchical PIN imported from the corresponding hierarchical LABEL" ... use for the ROOT schematic to make PINS - lets CONNECT by wires the subsheet symbols to the ROOT sheet connector - (checked by .NET file as /MIC1/out and /MIC2/out are LOCAL net names) - do DRC "BUG" in menu to check everything OFTEN ... - NOW each subsheet is in fact as "subroutine" wit defined "interface" and reusable fully in larger schematics !!! SYMBOLS WITH MULTIPLE UNITS - based on VIDEO #18 (28 minutes) https://www.youtube.com/watch?v=aa33Gme4hys&list=PL3by7evD3F51fKkyrUbH-PCdwPCWc9F8a&index=21 ---------------------------------------------------------------------------------------------- - !!! DAILY DRIVER IN CASE OF 74xx LOGIC CHIPS !!! - shown on 144pin FPGA Xilinx thing ... - place units of big FPGA on separate sheets in fact ... - demonstrated on simplified example of DUAL POTENTIOMETER - demonstrated on 2 OPAMP NE5532, having THIRD UNIT as POWER PINS !!!! (see digikey library variant has only 2 UNITS OPAMPS WITH POWER PINS) - comparison of ALL the options of organizin multiple UNITS - BE CAREFULL to do reanotation of individual units though in already laid out PCB design !!! - described ANOTATION SCHEMATIC dialog more for this... - annotation runs left-to-right and top-to-bottom !!! - so placing the individual units elsewhere causes REANNOTATIONS !!! - described more experiments how annotation behaves !!! - BE CAREFULL and NOT rename individual units as KiCad may lost trace of power units etc... (it CANT even find this in DRC !!!!!!) - REALLY CRAZY REANNOTATIONS in case of physically moving individual UNITS on the sheet !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! (possible in annotation dialog to set "RESET, but keep the order of multi-units parts) CREATING NEW SYMBOLS WITH MULTIPLE UNITS - based on VIDEO #19 (17 minutes) https://www.youtube.com/watch?v=3xUTpiKqVxc&list=PL3by7evD3F51fKkyrUbH-PCdwPCWc9F8a&index=22 ---------------------------------------------------------------------------------------------- - new Symbol properties have "Number of units per package" - noted "Units are not interchangeable" checkbox - GOOD IDEA TO HAVE THIS ALWAYS ENABLED !!! - described Symbol Editor "place pin" tool dialog - SELECT UNIT in editor menu CHECKBOX !!! - placed "foo" Symbol with 2 units, set as NOT INTERCHANGEABLE - mentioned possibility that while layouting PCB, may be easier to SWAP UNITS !!! (KiCad 5 does not automatically support that !!!) - placed "bar" Symbol with 2 units, set as INTERCHANGEABLE - !!! INCREDIBLY DISORIENTING AND CONFUSING RESULTS AFTER REANNOTATIONS !!! - !!! GENERALLY, REANNOTATIONS ARE EXTREMELLY DANGEROUS TO EXISTING PCB LAYOUTS !!! - read THIS MORE to understand (re)annontations usage https://www.circuitstate.com/tutorials/getting-started-with-kicad-version-6-beginners-tutorial-to-schematic-and-pcb-design/ 4 LAYER PCB LAYOUT - based on VIDEO #20 (12 minutes) https://www.youtube.com/watch?v=tiJApIz72tE&list=PL3by7evD3F51fKkyrUbH-PCdwPCWc9F8a&index=23 ---------------------------------------------------------------------------------------------- - starting with simple powered 1 cap circuit - PCB Editor: - menu Setup - Layer Setup - Copper layers = 4 - Preset Layer Groupings = where are parts, if only on one or both sides - layers FCu, Int1Cu, Int2Cu, BCu ... assigning to signals and/or power (usually internals are POWER VCC and GND) (John DOES NOT use autorouter on his boards, so leaves all layers as SIGNAL) - select Int1Cu layer - draw ZONE (the green icon/tool on right panel) ... set Int1Cu to GND net (close rect by click, double click or context CLOSE ZONE) - select Int2Cu layer - draw ZONE (the green icon/tool on right panel) ... set Int1Cu to VCC net (close rect by click, double click or context CLOSE ZONE) - "B" key to refill the zones !!! - generally is BEST to have board outside layers FILLED with Copper (to prevent THERMAL CONTRACTIONS - board can be "curved like pringles potato") - IT IS POSSIBLE to draw even NON VCC/GND lines on the internal layers to connect things together !!! LAYING OUT PARALLEL BUSES EXAMPLE !!! - based on VIDEO #21 (65 minutes) (Arduino NANO + MCP23017 + AT28C256) https://www.youtube.com/watch?v=3OEELxQewug&list=PL3by7evD3F51fKkyrUbH-PCdwPCWc9F8a&index=24 ----------------------------------------------------------------------------------------------- - USING 2 LAYER BOARD - placing all parts symbols - naming SCL and SDA nets on NANO - NOT ALWAYS easy to connect EEPROM chip D0 to MCP chip GP0 in PCB layout, often need to recode this is SOFTWARE, => COMPLICATED !!! - use "INSERT" key to repeat wires/net-names to underlying pins - VERY QUICK !!!!! - CHECKING the datasheet chip packages to TRY to layout the appropriate nets on EEPROM and MCP !!! - copying A0-A7 nets wires from 28C256 to GPA port of MCP first (iterative way to TRY routing this) - annotate schema - GENERATE netlist in here SCHEMA EDITOR - open PCB EDITOR and READ current netlist there - all parts but 28C256 have footprints so: - in schema editor, assign DIP28 footprint to the memory part symbol, check 3D by ALT+3 - in PCB EDITOR, layout footprints evenly - drav board outline in EdgeCuts layer - in schematic editor, copy more wires/nets from memory to MCP chip, (THINK about package pins of both by datasheet) - regenerate/save new netlist - in PCB EDITOR, READ current netlist (Keep everything on defaults) - DO ALL THIS ITERATIVELLY, by small chunks, to connect proper pins of memory chip to GOOD GP pins of MCP, allow clean SW !!! (repeate again ay to schematic editor and naming new nets/wires) (John is NOT using autorouter, KiCad CANT do automatic pins swaping, probably difficult for autorouter to work effectivelly ???) - now DATA BUS of memory goes to GPA port of second MCP - this will need to "FLIP" lines to MCP by VIAs and vertical bottoms !!! - setup OSHPark design rules in mils as 0.006 / 0.006 / 0.020 / 0.010 (also edit in dialog GLOBAL max limits !!!) - START ROUTING - BUT, menu Router - Interactive Router Settings - chenge mode form WALK AROUND to SHOVE (makes space as you route lines !!!) - HAVE GRID setting to 1 mil !!! for routing to be better !!! - route close paths first properly to SHOVE work better then for the longer - route longer paths evenly; it IS POSSIBLE to lay 2 thin traces between 2.54 DIP pins, but is better to lay ONLY ONE - as we have 2 LAYER board, on TOP draw ONLY horizontal lines, and n BOTTOM dra ONLY vertical lines - use AS SMALL VIAs AS POSSIBLE (lots of them, he now uses precise OSHPark for this...) - hit "V" to place VIAs ... - hit "D" to move VIAs ... - routing of LEFT set of data lines of memory chip to MCP using VIAs - demonstrated COMPARE of approach on left MCP (on top only) vs data traces from right MCP by VIAs and vertical lines on bottom layer !!! - menu Preferences - Display Options - possible to HIDE the 3D models to see entire board routing - SHOVE assisted routing allows to "make room" by moving already routed areas of PCB traces automatically, its visually gided during routing - to eliminate CROSTALLK, John routes only ONE data line between SCL/SDA serial pins, not two ... - forgotten space for blocking CAP between power lines of MCP chip - routing of remaining RIGHT set of data lines of memory chip to MCP using VIAs - IN FACT, finally, there ARE 2 thin traces around SCL/SDA anyway ... - routing both MCPs SCL/SDA at bottom of board through the VIAs to the Arduino NANO pins - consulting DATASHEET for EEPROM WRITE signals behavior, the SETUP and HOLD timing (so write ALL A/D OE/CE and then later make WE low pulse) (as WE signal is CRITICAL for proper operation, it is fortunatelly AWAY from other FAST signals on board for CROSSTALK) (unfortunatelly HIGH SPEED SCL/SDA will radiate into near data lines !!!) - SO, to maximally eliminate CROSSTALK, draw the SCL/SDA BCu (green) lines they way they cross at 90deg over data lines !!! - EVEN SO, John moves the data lines going between SCL/SDA totally AWAY by shifting things down on the board !!! (umm 2 data lines still near) (BUT, its NOT at MHz or even GHz speeds ... that has much higher energy...) - hit "V" to place VIAs ... - hit "D" to move VIAs ... - do the F.Cu layer polygon ZONE fill (forgotten any GNDs on schematic !!! - so add, regenerate netlist and read it PCB EDITOR) - edit GND ZONE properties to 10 mils for Clearance, Minimum width, Antipad clearance, and leave spoke at 20 mils) - tweaking filling of GND ZONES around entire board by moving SCL/SDA traces by moving their VIAs up (so hide zone, move, show zone, hit "B" to refill) - place some more VIAs to make better connection of grounds in thin filled areas PCB MOUNTING HOLES - based on VIDEO #22 (20 minutes) https://www.youtube.com/watch?v=tzOvvx7UPl4&list=PL3by7evD3F51fKkyrUbH-PCdwPCWc9F8a&index=25 ----------------------------------------------------------------------------------------------- - naive approach, use VIA and modify diameter ... NO !!! - instead "Add footprint" - search "Mounting hole" !!! - hit "B" to refill polygons - to EDIT, dont select the "pad" but select aside of pad (footprint properties) - lock footprint (or they will disappear after reloading netlist !!!) - edit pad and soldermask clearance to allow entire bolt head to be out of copper - check PCB MFG what overlap of soldermask allows - its also possible to place such part into schematic (its in fact documentation, and SOURCE for everything on PCB !!!) - there is also "MountingHole_Pad" symbol, as plated hole (PTH) for screw, usually on GND - also is there "MountingHole_Pad * VIA" for better connection to internal GND layer - !!! some MFGs CANNOT do NPTH, non plated holes !!! USING THE NET TIE - based on VIDEO #23 (12 minutes) https://www.youtube.com/watch?v=7uGGPNSqA-A&list=PL3by7evD3F51fKkyrUbH-PCdwPCWc9F8a&index=26 ----------------------------------------------------------------------------------------------- - use for separate GNDs, as digital GNDD and analog GNDA (at some SPECIFIC point connected) -